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» Operation and data mapping for CGRAs with multi-bank memory
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RTAS
2006
IEEE
14 years 1 months ago
Memory Footprint Reduction with Quasi-Static Shared Libraries in MMU-less Embedded Systems
Despite a rapid decrease in the price of solid state memory devices, system memory is still a very precious resource in embedded systems. The use of shared libraries is known to b...
Jaesoo Lee, Jiyong Park, Seongsoo Hong
JSA
2000
116views more  JSA 2000»
13 years 7 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
DAC
2004
ACM
14 years 8 months ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
DT
2006
113views more  DT 2006»
13 years 7 months ago
The Challenges of Synthesizing Hardware from C-Like Languages
at their abstractions are similar to data types and operations supplied by conventional processors. A core principle of BCPL is its memory model: an The Challenges of Synthesizing ...
Stephen A. Edwards
ICS
1999
Tsinghua U.
14 years 3 hour ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer