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EUROPAR
2008
Springer
13 years 9 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
ICCSA
2007
Springer
13 years 11 months ago
A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization
Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future System-on-Chi...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...
HPDC
2007
IEEE
14 years 2 months ago
A fast topology inference: a building block for network-aware parallel processing
Adapting to the network is the key to achieving high performance for communication-intensive applications, including scientific computing, data intensive computing, and multicast...
Tatsuya Shirai, Hideo Saito, Kenjiro Taura
HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
14 years 1 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...