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EUROPAR
2010
Springer
13 years 9 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
BMCBI
2006
114views more  BMCBI 2006»
13 years 9 months ago
A direct comparison of protein interaction confidence assignment schemes
Background: Recent technological advances have enabled high-throughput measurements of protein-protein interactions in the cell, producing large protein interaction networks for v...
Silpa Suthram, Tomer Shlomi, Eytan Ruppin, Roded S...
GLOBECOM
2006
IEEE
14 years 3 months ago
Bandwidth Constraint Models: A Performance Study with Preemption on Link Failures
— Bandwidth constraint models have been a topic of intense discussions at the IETF meetings. Three conventional methods have been described in informational IETF RFCs and their p...
Joshua B. Goldberg, Sukrit Dasgupta, Jaudelice Cav...
NOCS
2008
IEEE
14 years 3 months ago
Circuit-Switched Coherence
—Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, ...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....
GECCO
2003
Springer
129views Optimization» more  GECCO 2003»
14 years 2 months ago
Inherent Fault Tolerance in Evolved Sorting Networks
This poster paper summarizes our research on fault tolerance arising as a by-product of the evolutionary computation process. Past research has shown evidence of robustness emergin...
Rob Shepherd, James A. Foster