261 search results - page 12 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
DATE
2010
IEEE
14 years 19 days ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
ISQED
2003
IEEE
14 years 24 days ago
2003
IEEE
We present a new technique for generating compact dictionaries for cause-effect diagnosis in BIST. This approach relies on the use of three compact dictionaries: (i) D1, containin...
TCAD
2002
13 years 7 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...