261 search results - page 27 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
FCCM
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
MCS
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. A new optimization technique is proposed for classifiers fusion — Cooperative Coevolutionary Ensemble Learning (CCEL). It is based on a specific multipopulational evo...
VTS
1996
IEEE
14 years 27 days ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...