We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...
We consider a wireless sensor network in which sensors are grouped into clusters, each with its own cluster head (CH). Each CH collects data from sensors in its cluster and relays...
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...