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ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
14 years 1 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
ENTCS
2002
166views more  ENTCS 2002»
13 years 7 months ago
Translation and Run-Time Validation of Optimized Code
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...
MOBIHOC
2005
ACM
14 years 7 months ago
Power balanced coverage-time optimization for clustered wireless sensor networks
We consider a wireless sensor network in which sensors are grouped into clusters, each with its own cluster head (CH). Each CH collects data from sensors in its cluster and relays...
Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula
HPCA
1998
IEEE
13 years 11 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
HIPC
1999
Springer
13 years 11 months ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...