A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...
Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Kare...
—We present the design and implementation of a parallel exact inference algorithm on the Cell Broadband Engine (Cell BE). Exact inference is a key problem in exploring probabilis...
Skyline queries help users make intelligent decisions over complex data, where different and often conflicting criteria are considered. Current skyline computation methods are rest...
Ping Wu, Caijie Zhang, Ying Feng, Ben Y. Zhao, Div...
We investigate the universal characteristics of the simulated time horizon of the basic conservative parallel algorithm when implemented on regular lattices. This technique [1, 2]...
G. Korniss, M. A. Novotny, A. K. Kolakowska, H. Gu...