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» Optimal Scheduling of Dynamic Progressive Processing
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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 5 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
DATE
2004
IEEE
175views Hardware» more  DATE 2004»
14 years 6 days ago
Breaking Instance-Independent Symmetries in Exact Graph Coloring
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...
Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Kare...
JPDC
2010
137views more  JPDC 2010»
13 years 6 months ago
Parallel exact inference on the Cell Broadband Engine processor
—We present the design and implementation of a parallel exact inference algorithm on the Cell Broadband Engine (Cell BE). Exact inference is a key problem in exploring probabilis...
Yinglong Xia, Viktor K. Prasanna
EDBT
2006
ACM
191views Database» more  EDBT 2006»
14 years 8 months ago
Parallelizing Skyline Queries for Scalable Distribution
Skyline queries help users make intelligent decisions over complex data, where different and often conflicting criteria are considered. Current skyline computation methods are rest...
Ping Wu, Caijie Zhang, Ying Feng, Ben Y. Zhao, Div...
SAC
2002
ACM
13 years 8 months ago
Statistical properties of the simulated time horizon in conservative parallel discrete-event simulations
We investigate the universal characteristics of the simulated time horizon of the basic conservative parallel algorithm when implemented on regular lattices. This technique [1, 2]...
G. Korniss, M. A. Novotny, A. K. Kolakowska, H. Gu...