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HPDC
2007
IEEE
14 years 2 months ago
A fast topology inference: a building block for network-aware parallel processing
Adapting to the network is the key to achieving high performance for communication-intensive applications, including scientific computing, data intensive computing, and multicast...
Tatsuya Shirai, Hideo Saito, Kenjiro Taura
IDEAS
2007
IEEE
135views Database» more  IDEAS 2007»
14 years 2 months ago
Bitmap Index Design Choices and Their Performance Implications
Historically, bitmap indexing has provided an important database capability to accelerate queries. However, only a few database systems have implemented these indexes because of t...
Elizabeth J. O'Neil, Patrick E. O'Neil, Kesheng Wu
IPPS
2003
IEEE
14 years 1 months ago
The Case for Fair Multiprocessor Scheduling
Partitioning and global scheduling are two approaches for scheduling real-time tasks on multiprocessors. Though partitioning is sub-optimal, it has traditionally been preferred; t...
Anand Srinivasan, Philip Holman, James H. Anderson...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 1 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
14 years 2 days ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko