Sciweavers

979 search results - page 134 / 196
» Optimal instruction scheduling using integer programming
Sort
View
PLDI
1995
ACM
14 years 7 days ago
Storage Assignment to Decrease Code Size
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, ge...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...
DATE
2000
IEEE
94views Hardware» more  DATE 2000»
14 years 1 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
IWOMP
2009
Springer
14 years 3 months ago
Evaluating OpenMP 3.0 Run Time Systems on Unbalanced Task Graphs
The UTS benchmark is used to evaluate task parallelism in OpenMP 3.0 as implemented in a number of recently released compilers and run-time systems. UTS performs parallel search of...
Stephen Olivier, Jan Prins
NSDI
2008
13 years 11 months ago
Swift: A Fast Dynamic Packet Filter
This paper presents Swift, a packet filter for high performance packet capture on commercial off-the-shelf hardware. The key features of Swift include (1) extremely low filter upd...
Zhenyu Wu, Mengjun Xie, Haining Wang
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
14 years 2 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...