Sciweavers

979 search results - page 170 / 196
» Optimal instruction scheduling using integer programming
Sort
View
SIGARCH
2008
107views more  SIGARCH 2008»
13 years 8 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...
ACMICEC
2004
ACM
162views ECommerce» more  ACMICEC 2004»
14 years 2 months ago
Balanced matching of buyers and sellers in e-marketplaces: the barter trade exchange model
In this paper, we describe the operation of barter trade exchanges by identifying key techniques used by trade brokers to stimulate trade and satisfy member needs, and present alg...
Peter Haddawy, Namthip Rujikeadkumjorn, Khaimook D...
CODES
2006
IEEE
14 years 2 months ago
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
14 years 9 days ago
Compiler-driven FPGA-area allocation for reconfigurable computing
In this paper, we propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem o...
Elena Moscu Panainte, Koen Bertels, Stamatis Vassi...
ASPDAC
2008
ACM
69views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Fast, quasi-optimal, and pipelined instruction-set extensions
Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, th...
Ajay K. Verma, Philip Brisk, Paolo Ienne