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» Optimal instruction scheduling using integer programming
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122
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MICRO
2003
IEEE
142views Hardware» more  MICRO 2003»
15 years 7 months ago
Hardware Support for Control Transfers in Code Caches
Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when con...
Ho-Seop Kim, James E. Smith
115
Voted
DAC
2005
ACM
15 years 4 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
IPPS
2003
IEEE
15 years 7 months ago
Extending OpenMP to Support Slipstream Execution Mode
OpenMP has emerged as a widely accepted standard for writing shared memory programs. Hardware-specific extensions such as data placement are usually needed to improve the scalabi...
Khaled Z. Ibrahim, Gregory T. Byrd
INFOCOM
2012
IEEE
13 years 4 months ago
Truthful spectrum auction design for secondary networks
Abstract—Opportunistic wireless channel access by nonlicensed users has emerged as a promising solution for addressing the bandwidth scarcity challenge. Auctions represent a natu...
Yuefei Zhu, Baochun Li, Zongpeng Li
122
Voted
LCTRTS
2007
Springer
15 years 8 months ago
Scratchpad allocation for data aggregates in superperfect graphs
Existing methods place data or code in scratchpad memory, i.e., SPM by either relying on heuristics or resorting to integer programming or mapping it to a graph coloring problem. ...
Lian Li 0002, Quan Hoang Nguyen, Jingling Xue