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» Optimal integrated code generation for VLIW architectures
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ICC
2008
IEEE
139views Communications» more  ICC 2008»
14 years 2 months ago
Enabling Flexible Packet Filtering Through Dynamic Code Generation
— Despite its efficiency, the general approach of hardcoding protocol format descriptions in packet processing applications suffers from many limitations. Among the others, the l...
Olivier Morandi, Fulvio Risso, Mario Baldi, Andrea...
CODES
2006
IEEE
14 years 2 months ago
Retargetable code optimization with SIMD instructions
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...
Manuel Hohenauer, Christoph Schumacher, Rainer Leu...
CASES
2005
ACM
13 years 10 months ago
Hardware support for code integrity in embedded processors
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
Milena Milenkovic, Aleksandar Milenkovic, Emil Jov...
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
14 years 17 days ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
CASES
2007
ACM
14 years 12 days ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall