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» Optimal integrated code generation for VLIW architectures
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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 8 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
CORR
2011
Springer
142views Education» more  CORR 2011»
13 years 6 days ago
Taming Numbers and Durations in the Model Checking Integrated Planning System
The Model Checking Integrated Planning System (MIPS) has shown distinguished performance in the second and third international planning competitions. With its object-oriented fram...
Stefan Edelkamp
ASPDAC
2010
ACM
129views Hardware» more  ASPDAC 2010»
13 years 6 months ago
System-level development of embedded software
Abstract-- Embedded software plays an increasingly important role in implementing modern embedded systems. Development of embedded software, and of Hardware-dependent Software in p...
Gunar Schirner, Andreas Gerstlauer, Rainer Dö...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
13 years 6 days ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
CGO
2005
IEEE
14 years 2 months ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe