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» Optimal integrated code generation for VLIW architectures
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CGO
2003
IEEE
14 years 21 days ago
Dynamic Trace Selection Using Performance Monitoring Hardware Sampling
Optimizing programs at run-time provides opportunities to apply aggressive optimizations to programs based on information that was not available at compile time. At run time, prog...
Howard Chen, Wei-Chung Hsu, Dong-yuan Chen
DAC
1995
ACM
13 years 11 months ago
Synthesis of Software Programs for Embedded Control Applications
— Software components for embedded reactive real-time applications must satisfy tight code size and runtime constraints. Cooperating finite state machines provide a convenient i...
Massimiliano Chiodo, Paolo Giusto, Attila Jurecska...
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
13 years 11 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
DAC
2010
ACM
13 years 10 months ago
Efficient fault simulation on many-core processors
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
INFOCOM
2008
IEEE
14 years 1 months ago
iPack: in-Network Packet Mixing for High Throughput Wireless Mesh Networks
—A major barrier for the adoption of wireless mesh networks is severe limits on throughput. Many in-network packet mixing techniques at the network layer [1], [2], [3] as well as...
Richard Alimi, Erran L. Li, Ramachandran Ramjee, H...