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» Optimal integrated code generation for VLIW architectures
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EWSA
2004
Springer
14 years 23 days ago
ArchWare: Architecting Evolvable Software
This paper gives an overview of the ArchWare European Project1 . The broad scope of ArchWare is to respond to the ever-present demand for software systems that are capable of accom...
Flávio Oquendo, Brian Warboys, Ronald Morri...
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
COMCOM
2002
120views more  COMCOM 2002»
13 years 7 months ago
The Cyclone Server Architecture: streamlining delivery of popular content
Abstract-We propose a new webserver architecture optimized for delivery of large, popular files. Delivery of such files currently pose a scalability problem for conventional conten...
Stanislav Rost, John W. Byers, Azer Bestavros
LCTRTS
2009
Springer
14 years 2 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...
CC
2010
Springer
117views System Software» more  CC 2010»
14 years 2 months ago
Punctual Coalescing
Compilers use register coalescing to avoid generating code for copy instructions. For architectures with register aliasing such as x86, Smith, Ramsey, and Holloway (2004) presented...
Fernando Magno Quintão Pereira, Jens Palsbe...