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» Optimal integrated code generation for VLIW architectures
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ACMSE
2004
ACM
14 years 23 days ago
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
Swathi Tanjore Gurumani, Aleksandar Milenkovic
DAC
2005
ACM
14 years 8 months ago
Temperature-aware resource allocation and binding in high-level synthesis
Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with futu...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
TVLSI
2008
120views more  TVLSI 2008»
13 years 7 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
EMSOFT
2009
Springer
14 years 1 months ago
Clock-driven distributed real-time implementation of endochronous synchronous programs
An important step in model-based embedded system design consists in mapping functional specifications and their tasks/operations onto execution architectures and their ressources...
Dumitru Potop-Butucaru, Robert de Simone, Yves Sor...
VTC
2007
IEEE
161views Communications» more  VTC 2007»
14 years 1 months ago
Early Results on Hydra: A Flexible MAC/PHY Multihop Testbed
— Hydra is a flexible wireless network testbed being developed at UT Austin. Our focus is networks that support multiple wireless hops and where the network, especially the MAC,...
Ketan Mandke, Soon-Hyeok Choi, Gibeom Kim, Robert ...