379 search results - page 6 / 76 » Optimal loop parallelization for maximizing iteration-level ... |
119
Voted
MICRO
2005
IEEE
15 years 8 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
130
Voted
IEEEPACT
1998
IEEE
15 years 7 months ago
1998
IEEE
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...
123
Voted
IFL
2005
Springer
15 years 8 months ago
2005
Springer
With-loops are versatile array comprehensions used in the functional array language SaC to implement universally applicable array operations. We describe the fusion of with-loops a...
170
Voted
MICRO
1995
IEEE
15 years 6 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
144
Voted
ICS
2000
Tsinghua U.
15 years 6 months ago
2000
Tsinghua U.
From a software engineering perspective, the Java programming language provides an attractive platform for writing numerically intensive applications. A major drawback hampering i...