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ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 2 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...
ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
14 years 1 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
14 years 3 days ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
GECCO
2006
Springer
152views Optimization» more  GECCO 2006»
13 years 11 months ago
A combinatorial genetic algorithm for the configuration of the 2dF/AAOmega spectrograph at the anglo-Australian observatory
To help unravel the structure of the universe, astronomers have developed systems which observe large clusters of objects at the same time. One such system is the 2-degree field s...
Steven Manos, Geraint Lewis