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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
13 years 11 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
DLOG
2000
13 years 9 months ago
High Performance Reasoning with Very Large Knowledge Bases
In this contribution we present an empirical analysis of the performance of the ALCNHR+ description logic system RACE applied to TBoxes with a very large number of primitive conce...
Volker Haarslev, Ralf Möller
DLOG
2008
13 years 10 months ago
Taming the Infinite Chase: Query Answering under Expressive Relational Constraints
Answering queries posed over knowledge bases is a central problem in knowledge representation and database theory. In databases, query containment is one of the important query op...
Andrea Calì, Georg Gottlob, Michael Kifer
FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
14 years 20 days ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
DAC
2003
ACM
14 years 8 months ago
The synthesis of cyclic combinational circuits
Combinational circuits are generally thought of as acyclic structures. It is known that cyclic structures can be combinational, and techniques have been proposed to analyze cyclic...
Marc D. Riedel, Jehoshua Bruck