215 search results - page 27 / 43 » Optimization Techniques for Parallel Codes of Irregular Scie... |
159
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PPOPP
2005
ACM
15 years 10 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
157
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
107
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IPPS
2002
IEEE
15 years 9 months ago
2002
IEEE
Multipartitioning is a strategy for parallelizing computations that require solving 1D recurrences along each dimension of a multi-dimensional array. Previous techniques for multi...
137
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ICPPW
2005
IEEE
15 years 10 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
131
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CCGRID
2008
IEEE
15 years 11 months ago
2008
IEEE
Understanding the potential and implications of asymmetric multi-core processors for cluster computing is necessary, as these processors are rapidly becoming mainstream components...