96 search results - page 9 / 20 » Optimization of Combinational Logic Circuits Based on Compat... |
CORR
2010
Springer
13 years 7 months ago
2010
Springer
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
JCO
2011
13 years 2 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
24
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FPGA
2004
ACM
14 years 1 months ago
2004
ACM
In this paper, we introduce a reconfigurable fabric based around a new class of circuit element: the hybrid Hall effect (HHE) magnetoelectronic device. Because they incorporate a ...
FDTC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...