Sciweavers

208 search results - page 12 / 42
» Optimization of a Retargetable Functional Simulator for Embe...
Sort
View
CORR
2010
Springer
89views Education» more  CORR 2010»
13 years 7 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
SIES
2008
IEEE
14 years 1 months ago
Dynamic voltage and frequency scaling for optimal real-time scheduling on multiprocessors
Abstract— Not only system performance but also energy efficiency is critically important for embedded systems. Optimal real-time scheduling is effective to not only schedulabili...
Kenji Funaoka, Akira Takeda, Shinpei Kato, Nobuyuk...
CODES
2008
IEEE
14 years 1 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
14 years 7 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
SAMOS
2004
Springer
14 years 25 days ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich