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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 4 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
CODES
2000
IEEE
14 years 2 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
FOCI
2007
IEEE
14 years 1 months ago
An Investigation on the Compression Quality of aiNet
AiNet is an immune-inspired algorithm for data compression, i.e. the reduction of redundancy in data sets. In this paper we investigate the compression quality of aiNet. Therefore,...
Thomas Stibor, Jonathan Timmis
SIGMOD
2008
ACM
193views Database» more  SIGMOD 2008»
14 years 10 months ago
Efficient provenance storage
Scientific workflow systems are increasingly used to automate complex data analyses, largely due to their benefits over traditional approaches for workflow design, optimization, a...
Adriane Chapman, H. V. Jagadish, Prakash Ramanan
ESTIMEDIA
2008
Springer
13 years 11 months ago
A framework for memory-aware multimedia application mapping on chip-multiprocessors
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasric...