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CGO
2003
IEEE
15 years 9 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
COMPSAC
2004
IEEE
15 years 7 months ago
A Development Framework for Rapid Meta-Heuristics Hybridization
While meta-heuristics are effective for solving large-scale combinatorial optimization problems, they result from time-consuming trial-and-error algorithm design tailored to speci...
Hoong Chuin Lau, Wee Chong Wan, Min Kwang Lim, Ste...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 7 months ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 7 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
GECCO
2006
Springer
168views Optimization» more  GECCO 2006»
15 years 7 months ago
3D airspace sectoring by evolutionary computation: real-world applications
This paper presents a new method for 3D cutting of geometrical space with application to airspace sectoring. This problem comes from the air traffic management but the proposed me...
Daniel Delahaye, Stephane Puechmorel