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» Optimization via Parameter Mapping with Genetic Programming
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HPCA
2009
IEEE
14 years 9 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
CORR
2008
Springer
170views Education» more  CORR 2008»
13 years 8 months ago
To Broad-Match or Not to Broad-Match : An Auctioneer's Dilemma ?
We initiate the study of an interesting aspect of sponsored search advertising, namely the consequences of broad match- a feature where an ad of an advertiser can be mapped to a b...
Sudhir Kumar Singh, Vwani P. Roychowdhury
IPPS
1997
IEEE
14 years 23 days ago
A Tool for On-line Visualization and Interactive Steering of Parallel HPC Applications
Tools for parallel systems today range from specification over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
Sabine Rathmayer
ESANN
2004
13 years 10 months ago
Sparse LS-SVMs using additive regularization with a penalized validation criterion
This paper is based on a new way for determining the regularization trade-off in least squares support vector machines (LS-SVMs) via a mechanism of additive regularization which ha...
Kristiaan Pelckmans, Johan A. K. Suykens, Bart De ...
ICASSP
2010
IEEE
13 years 7 months ago
A symmetric adaptive algorithm for speeding-up consensus
Performing distributed consensus in a network has been an important research problem for several years, and is directly applicable to sensor networks, autonomous vehicle formation...
Daniel Thai, Elizabeth Bodine-Baron, Babak Hassibi