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» Optimizations for LTL Synthesis
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ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
15 years 10 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
115
Voted
LICS
2006
IEEE
15 years 10 months ago
Avoiding Determinization
Automata on infinite objects are extensively used in system specification, verification, and synthesis. While some applications of the automata-theoretic approach have been wel...
Orna Kupferman
CVPR
2008
IEEE
16 years 6 months ago
Automatic non-rigid registration of 3D dynamic data for facial expression synthesis and transfer
Automatic non-rigid registration of 3D time-varying data is fundamental in many vision and graphics applications such as facial expression analysis, synthesis, and recognition. De...
Sen Wang, Xianfeng David Gu, Hong Qin
CODES
2007
IEEE
15 years 10 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
CODES
2007
IEEE
15 years 10 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas