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DAC
2005
ACM
14 years 8 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
DAC
2000
ACM
14 years 8 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
DCC
2008
IEEE
14 years 7 months ago
Drift Characterization of Intra Prediction and Quantization in H.264
The combination of intra prediction, transform, and quantization in the H.264/AVC video coding standard offers high compression performance in picture areas where inter prediction...
Athanasios Leontaris, Alexis M. Tourapis
IPSN
2005
Springer
14 years 1 months ago
XYZ: a motion-enabled, power aware sensor node platform for distributed sensor network applications
— This paper describes the XYZ, a new open-source sensing platform specifically designed to support our experimental research in mobile sensor networks. The XYZ node is designed...
Dimitrios Lymberopoulos, Andreas Savvides