1251 search results - page 32 / 251 » Optimizing Compilation of CLP(R) |
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
CASES
2006
ACM
14 years 2 months ago
2006
ACM
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
CP
2008
Springer
13 years 10 months ago
2008
Springer
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
PLDI
2011
ACM
12 years 11 months ago
2011
ACM
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
In recent years, several approaches have been proposed to use profile information in compiler optimization. This profile information can be used at the source level to guide loo...