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ICCAD
2006
IEEE
122views Hardware» more  ICCAD 2006»
14 years 7 months ago
Fill for shallow trench isolation CMP
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical planarization (CMP) to remove excess of deposited oxide and attain a planar...
Andrew B. Kahng, Puneet Sharma, Alexander Zelikovs...
ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
14 years 7 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
SOSP
2001
ACM
14 years 7 months ago
Resilient Overlay Networks
A Resilient Overlay Network (RON) is an architecture that allows distributed Internet applications to detect and recover from path outages and periods of degraded performance with...
David G. Andersen, Hari Balakrishnan, M. Frans Kaa...
SOSP
2005
ACM
14 years 7 months ago
THINC: a virtual display architecture for thin-client computing
Rapid improvements in network bandwidth, cost, and ubiquity combined with the security hazards and high total cost of ownership of personal computers have created a growing market...
Ricardo A. Baratto, Leonard N. Kim, Jason Nieh
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 7 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
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