244 search results - page 11 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
RSP
2005
IEEE
14 years 1 months ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
ASPLOS
2000
ACM
14 years 4 days ago
2000
ACM
The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect betw...
JCP
2008
13 years 7 months ago
2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...
ENTCS
2002
13 years 7 months ago
2002
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...