244 search results - page 38 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded ...
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applic...
SEMWEB
2010
Springer
13 years 5 months ago
2010
Springer
OWL 2 RL was standardized as a less expressive but scalable subset of OWL 2 that allows a forward-chaining implementation. However, building an enterprise-scale forward-chaining ba...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
CASES
2004
ACM
14 years 1 months ago
2004
ACM
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...