Sciweavers

165 search results - page 5 / 33
» Optimizing Matrix Multiplication on Heterogeneous Reconfigur...
Sort
View
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 1 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
TC
2008
13 years 7 months ago
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid adva...
Ling Zhuo, Viktor K. Prasanna
DATE
2009
IEEE
85views Hardware» more  DATE 2009»
14 years 1 months ago
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
ICIP
2005
IEEE
14 years 8 months ago
A reconfigurable multi-camera architecture for high resolution objects analysis
In this paper, a multi-camera architecture is presented for heterogeneous targets analysis and tracking. The proposed system can be switched in various configurations enabling aut...
Luca Marchesotti, Stefano Piva, Andrea F. Cattoni,...
ICASSP
2011
IEEE
12 years 10 months ago
Image editing based on Sparse Matrix-Vector multiplication
This paper presents a unified model for image editing in terms of Sparse Matrix-Vector (SpMV) multiplication. In our framework, we cast image editing as a linear energy minimizat...
Ying Wang, Hongping Yan, Chunhong Pan, Shiming Xia...