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» Optimizing Memory Accesses For Spatial Computation
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PCI
2005
Springer
14 years 1 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
SPAA
1997
ACM
13 years 12 months ago
Accessing Nearby Copies of Replicated Objects in a Distributed Environment
Consider a set of shared objects in a distributed network, where several copies of each object may exist at any given time. To ensure both fast access to the objects as well as e ...
C. Greg Plaxton, Rajmohan Rajaraman, Andréa...
IPPS
2009
IEEE
14 years 2 months ago
Scalable RDMA performance in PGAS languages
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
Montse Farreras, George Almási, Calin Casca...
ICNP
2006
IEEE
14 years 1 months ago
Benefit-based Data Caching in Ad Hoc Networks
—Data caching can significantly improve the efficiency of information access in a wireless ad hoc network by reducing the access latency and bandwidth usage. However, designing e...
Bin Tang, Himanshu Gupta, Samir R. Das
ICS
2010
Tsinghua U.
13 years 10 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...