2932 search results - page 117 / 587 » Optimizing Memory System Performance for Communication in Pa... |
ESA
1998
Springer
14 years 27 days ago
1998
Springer
Abstract. Data sets in large applications are often too massive to t completely inside the computer's internal memory. The resulting input output communication or I O between ...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
HCW
2000
IEEE
14 years 1 months ago
2000
IEEE
A heuristic algorithm that maps data-processing tasks onto heterogeneous resources (i.e., processors and links of various capacities) is presented. The algorithm tries to achieve ...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
Previous studies of application usage show that the performance of collective communications are critical for high-performance computing and are often overlooked when compared to ...
IEEEPACT
2007
IEEE
14 years 3 months ago
2007
IEEE
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...