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IPPS
2007
IEEE
14 years 2 months ago
Performance Evaluation of two Parallel Programming Paradigms Applied to the Symplectic Integrator Running on COTS PC Cluster
There are two popular parallel programming paradigms available to high performance computing users such as engineering and physics professionals: message passing and distributed s...
Lorena B. C. Passos, Gerson H. Pfitscher, Tarcisio...
PPOPP
2010
ACM
14 years 5 months ago
Modeling transactional memory workload performance
Transactional memory promises to make parallel programming easier than with fine-grained locking, while performing just as well. This performance claim is not always borne out bec...
Donald E. Porter, Emmett Witchel
IPPS
1998
IEEE
14 years 7 days ago
Memory Hierarchy Management for Iterative Graph Structures
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
Ibraheem Al-Furaih, Sanjay Ranka
IEEEPACT
2002
IEEE
14 years 27 days ago
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications
Data parallel compilers have long aimed to equal the performance of carefully hand-optimized parallel codes. For tightly-coupled applications based on line sweeps, this goal has b...
Daniel G. Chavarría-Miranda, John M. Mellor...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 5 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou