43 search results - page 8 / 9 » Optimizing Nested Loops with Iterational and Instructional R... |
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
PLDI
2005
ACM
14 years 1 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...