Sciweavers

2703 search results - page 141 / 541
» Optimizing memory transactions
Sort
View
ICMAS
1998
13 years 11 months ago
Simulating Value Chain Coordination with Artificial Life Agents
The increasing use of information technology within and between companies yields changes in the predominant coordination mechanisms. On one hand it is argued that we witness an ov...
Torsten Eymann, Boris Padovan, Detlef Schoder
CC
2008
Springer
144views System Software» more  CC 2008»
14 years 1 days ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
CCR
2004
153views more  CCR 2004»
13 years 10 months ago
Tree bitmap: hardware/software IP lookups with incremental updates
IP address lookup is challenging for high performance routers because it requires a longest matching prefix at speeds of up to 10 Gbps (OC-192). Existing solutions have poor updat...
Will Eatherton, George Varghese, Zubin Dittia
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
14 years 4 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
CCGRID
2007
IEEE
14 years 4 months ago
Revisit of View-Oriented Parallel Programming
Traditional parallel programming styles have many problems which hinder the development of parallel applications. The message passing style can be too complex for many programmers...
Z. Huang, W. Chen