Sciweavers

2703 search results - page 153 / 541
» Optimizing memory transactions
Sort
View
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
12 years 15 days ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
ISVLSI
2005
IEEE
69views VLSI» more  ISVLSI 2005»
14 years 3 months ago
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access con...
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, E...
CORR
2006
Springer
78views Education» more  CORR 2006»
13 years 10 months ago
On the Fading Number of Multiple-Input Single-Output Fading Channels with Memory
We derive new upper and lower bounds on the fading number of multiple-input single-output (MISO) fading channels of general (not necessarily Gaussian) regular law with spatial and ...
Stefan M. Moser
POPL
2002
ACM
14 years 10 months ago
An efficient profile-analysis framework for data-layout optimizations
Data-layout optimizations rearrange fields within objects, objects within objects, and objects within the heap, with the goal of increasing spatial locality. While the importance ...
Rastislav Bodík, Shai Rubin, Trishul M. Chi...
JSAC
2008
124views more  JSAC 2008»
13 years 10 months ago
On the design of globally optimal communication strategies for real-time noisy communication systems with noisy feedback
Abstract--A real-time communication system with noisy feedback is considered. The system consists of a Markov source, forward and backward discrete memoryless channels, and a recei...
Aditya Mahajan, Demosthenis Teneketzis