2703 search results - page 188 / 541 » Optimizing memory transactions |
105
Voted
IPPS
2000
IEEE
15 years 7 months ago
2000
IEEE
Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and s...
128
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HPCA
1999
IEEE
15 years 6 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
IPPS
1998
IEEE
15 years 6 months ago
1998
IEEE
We study the problem of mapping the N nodes of a complete t-ary tree on M memory modules so that they can be accessed in parallel by templates, i.e. distinct sets of nodes. Typica...
143
Voted
CODES
2011
IEEE
14 years 2 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
116
Voted
ENGL
2008
15 years 2 months ago
2008
This paper proposes the LQ-Servo controller for AQM (Active Queue Management) routers. The proposed controller structure is made by taking a traditional servo mechanism based on Li...