2703 search results - page 196 / 541 » Optimizing memory transactions |
101
Voted
CAV
2012
Springer
13 years 5 months ago
2012
Springer
The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying th...
108
Voted
DSD
2009
IEEE
15 years 9 months ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
118
Voted
ICS
2009
Tsinghua U.
15 years 9 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
136
click to vote
SP
2008
IEEE
15 years 9 months ago
2008
IEEE
Attacks often exploit memory errors to gain control over the execution of vulnerable programs. These attacks remain a serious problem despite previous research on techniques to pr...
103
Voted
IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
Audio search plays an important role in analyzing audio data and retrieving useful audio information. In this paper, a Partially Overlapping Block-Parallel Active Search method (P...