2703 search results - page 56 / 541 » Optimizing memory transactions |
IESS
2009
Springer
13 years 6 months ago
2009
Springer
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
ASPDAC
2006
ACM
14 years 12 days ago
2006
ACM
- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
TAICPART
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract. Unit testing in the presence of side eects requires the construction of a suitable test xture before each test run. We consider the problem of providing test xtures fo...
ISMIS
2005
Springer
14 years 2 months ago
2005
Springer
We address the problem of loading transactional datasets into main memory and estimating the density of such datasets. We propose BoolLoader, an algorithm dedicated to these tasks;...
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...