2703 search results - page 82 / 541 » Optimizing memory transactions |
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
CONCURRENCY
2006
13 years 8 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
NPC
2005
Springer
14 years 2 months ago
2005
Springer
This paper focuses on the Cyclops64 computer architecture and presents an analytical model and performance simulation results for the preloading and loop unrolling approaches to op...
GECCO
2009
Springer
13 years 6 months ago
2009
Springer
This paper describes a general scheme to convert sequential ant-based algorithms into parallel shared memory algorithms. The scheme is applied to an ant-based algorithm for the ma...
ISCA
2008
IEEE
14 years 3 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...