2703 search results - page 93 / 541 » Optimizing memory transactions |
MICRO
2007
IEEE
14 years 3 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
CONCUR
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. Reactive systems are often modelled as two person antagonistic games where one player represents the system while his adversary represents the environment. Undoubtedly, t...
TPDS
1998
13 years 8 months ago
1998
This paper presents a new compiler optimization algorithm that parallelizes applications for symmetric, sharedmemory multiprocessors. The algorithm considers data locality, parall...
VLSI
2005
Springer
14 years 2 months ago
2005
Springer
1 The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automa...
ESA
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. In this paper we study the external memory planar point enclosure problem: Given N axis-parallel rectangles in the plane, construct a data structure on disk (an index) su...