2048 search results - page 292 / 410 » Optimizing pipelines for power and performance |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
GECCO
2005
Springer
14 years 1 months ago
2005
Springer
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with significant run times. Two parallel models for GA are presented for VLSI cell placemen...
GECCO
2010
Springer
14 years 26 days ago
2010
Springer
In this paper, we compare the (1+1)-CMA-ES to the (1+2s m)CMA-ES, a recently introduced quasi-random (1+2)-CMAES that uses mirroring as derandomization technique as well as a sequ...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
VLSISP
2008
13 years 8 months ago
2008
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...