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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
14 years 1 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
14 years 1 days ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun
IPPS
2010
IEEE
13 years 5 months ago
Performance and energy optimization of concurrent pipelined applications
In this paper, we study the problem of finding optimal mappings for several independent but concurrent workflow applications, in order to optimize performance-related criteria tog...
Anne Benoit, Paul Renaud-Goud, Yves Robert
IC
2004
13 years 9 months ago
Optimizing Performance of Web Services with Chunk-Overlaying and Pipelined-Send
The performance of a Web service is primarily dependent on the design and implementation of its SOAP toolkit. SOAP is widely implemented using HTTP as the transport protocol and X...
Nayef Abu-Ghazaleh, Madhusudhan Govindaraju, Micha...
LCTRTS
2001
Springer
14 years 5 days ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh