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» Optimizing the FPGA Implementation of HRT Systems
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FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
14 years 2 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
DATE
2000
IEEE
89views Hardware» more  DATE 2000»
14 years 1 months ago
A System-Level Synthesis Algorithm with Guaranteed Solution Quality
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Ch...
FCCM
2004
IEEE
103views VLSI» more  FCCM 2004»
14 years 16 days ago
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
Jian Liang, Russell Tessier, Dennis Goeckel
ARC
2007
Springer
140views Hardware» more  ARC 2007»
14 years 24 days ago
Reconfigurable Computing for Accelerating Protein Folding Simulations
Abstract. This paper presents a methodology for the design of a reconfigurable computing system applied to a complex problem in molecular Biology: the protein folding problem. An e...
Nilton B. Armstrong, Heitor S. Lopes, Carlos R. Er...
EUC
2005
Springer
14 years 2 months ago
Realtime H.264 Encoding System Using Fast Motion Estimation and Mode Decision
Abstract. H.264 provides various useful features such as improved coding efficiency and error robustness. These features enable mobile device to adopt H.264/AVC standard to achieve...
Byeong-Doo Choi, Min-Cheol Hwang, Jun-Ki Cho, Jin-...