1990 search results - page 29 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
CN
2002
13 years 7 months ago
2002
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
EUROPAR
2001
Springer
14 years 3 days ago
2001
Springer
A swap instruction, which exchanges a value in memory with a value of a register, is available on many architectures. The primary application of a swap instruction has been for pro...
SOCA
2010
IEEE
13 years 5 months ago
2010
IEEE
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...