On High-Bandwidth Data Cache Design for Multi-Issue Processors

Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The number of instructions that must be processed (including incorrectly predicted ones) will approach 16 or more per cycle. Since memory operations account for about a third of all instructions executed, these systems will have to support multiple data references per cycle. In this paper, we explore reference stream characteristics to determine how best to meet the need for ever increasing access rates. We identify limitations of existing multiported cache designs and propose a new structure, the Locality-Based Interleaved Cache (LBIC), to exploit the characteristics of the data reference stream while approaching the economy of traditional multi-bank cache design. Experimental results show that the LBIC structure is capable of outperforming current multi-ported approaches.

• Type: Conference
• Year: 1997
• Where: MICRO
• Authors: Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
• Keywords: Cache, Cache Design, Cache Memory System, Hardware, MICRO 1997