Sciweavers

1990 search results - page 68 / 398
» Optimizing the Instruction Cache Performance of the Operatin...
Sort
View
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 2 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
HPCA
1999
IEEE
14 years 13 hour ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
TCAD
2008
88views more  TCAD 2008»
13 years 7 months ago
Self-Adaptive Data Caches for Soft-Error Reliability
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
CP
2008
Springer
13 years 9 months ago
An Application of Constraint Programming to Superblock Instruction Scheduling
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
Abid M. Malik, Michael Chase, Tyrel Russell, Peter...
HICSS
2007
IEEE
382views Biometrics» more  HICSS 2007»
14 years 2 months ago
Using Computer Simulation in Operating Room Management: Impacts on Process Engineering and Performance
Operating rooms are regarded as the most costly hospital facilities. Due to rising costs and decreasing reimbursements, it is necessary to optimize the efficiency of the operating...
Andre S. Baumgart, Anja Zöller, Christof Denz...