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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
11 years 11 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
14 years 15 days ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
13 years 6 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
VEE
2005
ACM
150views Virtualization» more  VEE 2005»
14 years 2 months ago
Diagnosing performance overheads in the xen virtual machine environment
Virtual Machine (VM) environments (e.g., VMware and Xen) are experiencing a resurgence of interest for diverse uses including server consolidation and shared hosting. An applicati...
Aravind Menon, Jose Renato Santos, Yoshio Turner, ...
DAC
2009
ACM
14 years 1 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers